Firmware
Create your project, verify your D.F.T, and then generate your test program
- Integrated Development Environment ( I.D.E )
- DFT mode ( Design For Test ) or Automatic Test Program Generation ( ATPG )
- CAD sysem inout : Cadence, Edif, FabMaster
- Boundary Scan path analysis
- Flashs memories, and iSP components downloading included
- Testability reports, tested pins and nets list / un-tested...
- CAD data Viewer, net-list merger, non-JTAG components models library...
- Data Packager ( For safe transfert between users and backup )
Lets's use your Boundary Scan test program
- Fail messages in French/English language with pin and net diagnostic level
- Free Runtime : as many test places as you want
Migrate into the "High level standard production gate"
- Set up you test program in one standard production oriented environnement
- Organize your test reports ( serial number, date, results … )
- Customize this high level interface ( user rights administration)
Debug with the TH_DEBUG graphical tool your board
- Optimise your test program with tuned patterns :
- Choose the pins to be driven...
- ... then draw chronograms ( Waveform view (chronogram) or Timing view (Excel like))
- Several test's modes are available ( single, burst, step by step, loop...)
- Automatic conflict management
- Easily Integrate the tuned patterns in the ATPG test program
Raspberry pi powered