T H _ J T A G


Create your project, verify your D.F.T, and then generate your test program

  • Integrated Development Environment ( I.D.E )
  • DFT mode ( Design For Test ) or Automatic Test Program Generation ( ATPG )
  • CAD sysem inout : Cadence, Edif, FabMaster
  • Boundary Scan path analysis
  • Flashs memories, and iSP components downloading included
  • Testability reports, tested pins and nets list / un-tested...
  • CAD data Viewer, net-list merger, non-JTAG components models library...
  • Data Packager ( For safe transfert between users and backup )